The key component of digital storage oscilloscope -- input front-end mode/number converter is usually a high-speed integrated circuit designed and specially designed by measuring instrument companies. It is not for sale on the market. For example, TeK's ADC with bandwidth above 500MHz used in TDS5000 series is jointly developed and manufactured by TeK and IBM.
Maximum sampling rate -2GS/S
Road maximum resolution -10 bits
Analog input voltage and impedance - 500 mv, 100 Ω (difference), 50 Ω (single side).
Road analog input bandwidth -3.3GHz
High frequency characteristic of 1GHz -- 7.8 significant digits, signal to noise ratio 51dB, clutter free dynamic range -55db,
Channel adjustment function -ADC gain, sampling delay, effective data output, overrange indicating output, 1:4 multiplex signal output.
Power supply voltage -- 5V, -2.2v, 3.3v, 2.5vp, power dissipation: 6.5w
Road closure - - EBGA317, 25 x 35 mm
Road operating temperature -0℃~90℃(civil grade)-20℃~110℃(industrial grade)
Input signal Vin to AT84AS004 chip is fed into quantizer and logic circuit by sampling and holding circuit S/H, and A/D conversion process is realized under the action of clock input CLR, sampling delay adjustment SDA, pattern generator significant bit PGEB and reset pulse DRRB. The obtained A/D data output is amplified by demultiplexer DMUX and low-voltage differential buffer LVDS to form 4-way output ports A, B, C and D. Four groups of 10-digit digital signals are output for storage, DSP and other data processing.The chip's adjustment signal also includes built-in self-test BIST, asynchronous reset ASYNRST, gain adjustment GA, binary and grayscale code selection B/GB, SLEEP state SLEEP, etc.
AT84S004 is the ADC with the highest frequency index on the market.First, the sampling rate reaches 2GS/S, and the analog input bandwidth is 3.3GHz. According to the principle of sampling, the Δ F Fs / 2 or less a Fs the real-time bandwidth should be less than or equal to the sampling rate.The chip Fs=2GS/s, obtain delta F=1GHz, that is, the first Nyquist region in the 1GHz below, the second Nyquist region extended to 2GHz. In order to avoid waveform confusion, the digital storage oscilloscope only USES the first Nyquist region, but, when the dual-frequency communication application, may enter the second Nyquist region, because needs for the wider input bandwidth. Secondly, the effective bits at 1GHz are 7.8 bits instead of 10 bits. As the clock frequency increases and the voltage comparator level is not stable, the resolution of high frequency will decline from 10 bits to 7.8 bits.Most digital storage oscilloscopes on the market have a resolution of 8 bits.It's less than 7 bits at high frequencies.Also, the chip provides 1:2 and 1:4 multiplex digital output, which is very advantageous for back-end data processing. Flash and DSP with lower clock can be used to reduce circuit cost.